Analog Timing Recovery for a Noise-Predictive DFE∗
نویسندگان
چکیده
A timing recovery architecture and its CMOS implementation are described for a noise-predictive decisionfeedback equalizer (NPDFE). The 0.5μm CMOS prototype includes timing recovery and the NPDFE and operates at 160Mbps. The timing recovery blocks dissipate 27mW from 3.3V, occupy 0.2 mm, and achieve a rms jitter of 50 ps, which is 0.8% of a bit period.
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